By David A. Patterson
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Additional resources for Computer Organization and Design, Third Edition: The Hardware/Software Interface, Third Edition
5 Execution Configuration . . . . . . . . . . 1 Thread-Level Parallelism . . . . . . . . . 1 Shared Memory . . . . . . . . . 2 Instruction-Level Parallelism . . . . . . . . CUDA Fortran for Scientists and Engineers. 00003-1 © 2014 Elsevier Inc. All rights reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Instruction Optimization . . . 1 Device Intrinsics . . . . 1 Directed Rounding . 2 C Intrinsics . . . 3 Fast Math Intrinsics . 2 Compiler Options . . . . 3 Divergent Warps . . . . 7 Kernel Loop Directives .
107 108 108 108 108 108 109 110 113 113 114 In the previous chapter we discussed how we can use timing information to determine the limiting factor of kernel execution. Many science and engineering codes turn out to be bandwidth bound, which is why we devote the majority of this relatively long chapter to memory optimization. CUDA-enabled devices have many different memory types, and to program effectively, we need to use these memory types efficiently. Data transfers can be broken down in to two main categories: data transfers between host and device memories, and data transfers between different memories on the device.