Download Cache and Memory Hierarchy Design. A Performance Directed by Steven A. Przybylski PDF

By Steven A. Przybylski

An authoritative booklet for and software program designers. Caches are via a long way the best and superior mechanism for bettering desktop functionality. This cutting edge publication exposes the features of performance-optimal unmarried and multi-level cache hierarchies through forthcoming the cache layout strategy in the course of the novel standpoint of minimizing execution instances. It provides valuable information at the relative functionality of a large spectrum of machines and provides empirical and analytical reviews of the underlying phenomena. This publication can help laptop pros get pleasure from the effect of caches and permit designers to maximise functionality given specific implementation constraints.

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Extra resources for Cache and Memory Hierarchy Design. A Performance Directed Approach

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Not only are there three more free variables for each additional level in the hierarchy, but the functions that relate the various cache parameters to the execution time transcend levels in the hierarchy: the miss penalty at one level of the cache is dependent on the speed and mean access time of the downstream cache, and conversely the local miss ratio at one level is dependent on the miss rate of the upstream cache. Despite the additional complexity, multi-level hierarchies are important because frequently execution times can be substantially lowered by increasing the depth of the hierarchy [Chow 76, Short 87].

The primary organizational characteristics that determine the miss ratio are a cache's size, C, its associativity, A, the number of sets, S, and the block size, B. The choices of the fetch and write strategies introduce other factors into the miss ratio equation, but these will be ignored temporarily for the sake of conceptual clarity. 1] It is generally accepted that as any of these parameters increases, the miss rate decreases, but that after a certain point, further increases do little good (See Figure 3-1).

Appendix B illustrates that the the write buffers have a significant effect on the contributions of writes to the execution time, so that modelling them accurately is crucial to the credibility of the empirical results. In summary, the credibility of the trace-driven simulation results presented in Chapters 4 and 5 stem from the strength of all three important components: an accurate simulator, realistic system models and representative input traces. 10 The bulk of the simulations were done on an MIPS Computer System's M/1000, a DEC Western Research Lab Titan and about 20 MicroVax lis scattered around the Center for Integrated Systems at Stanford.

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